八选一数据选择器用VHDL设计方法。

library ieee;
use ieee.std_logic_1164.all;
entity mux8_1 is
port(kd:in std_logic_vector(2 downto 0);
input:in std_logic_vector(7 downto 0);
output:out std_logic);
end;
architecture art of mux8_1 is
begin
process(kd,input)
begin
if kd="000" then
output<=input(0);
elsif kd="001" then
output<=input(1);
elsif kd="010" then
output<=input(2);
elsif kd="011" then
output<=input(3);
elsif kd="100" then
output<=input(4);
elsif kd="101" then
output<=input(5);
elsif kd="110" then
output<=input(6);
elsif kd="111" then
output<=input(7);
else null;
end if;
end process;
end art;

library
ieee;
use
ieee.std_logic_1164.all;
entity
mux8_1
is
port(kd:in
std_logic_vector(2
downto
0);
input:in
std_logic_vector(7
downto
0);
output:out
std_logic);
end;
architecture
art
of
mux8_1
is
begin
process(kd,input)
begin
if
kd="000"
then
output<=input(0);
elsif
kd="001"
then
output<=input(1);
elsif
kd="010"
then
output<=input(2);
elsif
kd="011"
then
output<=input(3);
elsif
kd="100"
then
output<=input(4);
elsif
kd="101"
then
output<=input(5);
elsif
kd="110"
then
output<=input(6);
elsif
kd="111"
then
output<=input(7);
else
null;
end
if;
end
process;
end
art;