library ieee;
use ieee.std_logic_1164.all;
entity div2 is
port (clk:in std_logic;
q:out std_logic);
end div2;
architecture behave of div2 is
signal q_n :std_logic;
begin
process(clk)
begin
if (clk'event AND clk='1') then
q <= q_n;
q_n <= NOT q_n;
end if;
end process;
end behave;
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