LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITYdecoder_tb IS
ENDENTITY;
ARCHITECTUREbehaviour OFdecoder_tb IS
COMPONENT decoder IS
PORT(a,b,c,e1,e2,e3: INSTD_LOGIC;
y : OUTSTD_LOGIC_VECTOR(7 DOWNTO 0));
ENDCOMPONENT;
--定义测试信号
SIGNALa,b,c,e1,e2,e3: STD_LOGIC;
SIGNALy : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
U1: decoder PORT MAP(a,b,c,e1,e2,e3,y);--元件实例化
test_vector:PROCESS--测试进程
BEGIN
e1<='0';
e2<='0';
e3<='1';
a<='1';--测试输入101
b<='0';
c<='1';
WAIT FOR 100 ns;--等待一段时间变换测试向量,这样才能在波形图中看到输出
a<='0';--测试输入011
b<='1';
c<='1';
WAIT FOR 1000 ns;
END PROCESS;
END behaviour;
--百度一把testbench就能找到很多教写testbench的文章