如何用VHDL语言编写三选一数据选择器

二选一选择器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX21 IS
PORT(
A:IN STD_LOGIC;
B:IN STD_LOGIC;
S:IN STD_LOGIC;
Y:OUT STD_LOGIC
);
END ENTITY MUX21;
ARCHITECTURE MUX21A OF MUX21 IS
BEGIN
PROCESS(S,A,B) BEGIN
IF S='0' THEN Y<=A;
ELSE Y<=B;
END IF;
END PROCESS;
END MUX21A;

顶层文件
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX31 IS
PORT(A1,A2,A3,S0,S1:IN STD_LOGIC;
OUTY:OUT STD_LOGIC);
END MUX31;
ARCHITECTURE MUX31A OF MUX31 IS
SIGNAL TMP:STD_LOGIC;
COMPONENT MUX21
PORT(A,B,S:IN STD_LOGIC; Y:OUT STD_LOGIC);
END COMPONENT;

BEGIN
U0:MUX21 PORT MAP(A=>A2,B=>A3,S=>S0,Y=>TMP);
U1:MUX21 PORT MAP(A=>A1,B=>TMP,S=>S1,Y=>OUTY);
END MUX31A ;

library ieee;
use ieee.std_logic_1164.all;
entity sxy is
port(
d0,d1,d2:in std_logic;
en:in std_logic;
a:in std_logic_vector(1 downto 0);
y:out std_logic
);
end sxy;
architecture a of sxy is
begin
process(d0,d1,d2,en,a)
begin
if en='0' then y<='0';
else
case a is
when "00"=>
y<=d0;
when "01"=>
y<=d1;
when "10"=>
y<=d2;
when others=>
y<='0';
end case;
end if;
end process;
end a;