怎样用VHDL语言程序设计一个带有异步复位的同步16进制加法计数器

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY cnt16 IS
PORT ( clk : IN std_logic;
rst: IN std_logic;
en: IN std_logic;
cout : OUT std_logic );
END cnt16;
ARCHITECTURE behav OF cnt16 IS
signal bcd :std_logic_vector(3 DOWNTO 0);
BEGIN
PROCESS(clk, rst, en)
VARIABLE cqi : std_logic_vector(3 DOWNTO 0);
BEGIN
IF rst = '1' THEN cqi := (OTHERS =>'0') ;
ELSIF clk'event AND clk='1' THEN
IF en = '1' THEN
IF cqi = "1111" THEN cqi :="0000";
ELSE cqi := cqi + 1;
END IF;
END IF;
END IF;
IF cqi = "1111" THEN cout <= '1';
ELSE cout <= '0';
END IF;
bcd<=cqi;
END PROCESS;
END;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity cnt16 is port
(rst : in std_logic;
clk : in std_logic;
cntout : out std_logic_vector(3 downto 0));

end cnt16;

architecture a of cnt16 is
signal cnt : integer:=0 ;
begin
process(rst, clk)
begin
if( rst = '1') then
cnt <= 0;
elsif rising_edge(clk) then
if cnt < 16 then
cnt <= cnt +1;
else
cnt <= 0;
end if;
end if;
end process;
cntout <= conv_std_logic_vector(cnt, 4);
end a;