用VHDL语言设计一个共阴极七段数码管的译码电路，急求大神解答，高分求助！！！不要粘贴复制的

74LS49是一个7段译码器，其VHDL描述如下：
LIBRARYIEEE;
USE IEEE.Std_logic_1164.ALL;
ENTITYls49 IS
PORT(bl: IN Std_logic;
bi: IN Std_logic_vector(3 DOWNTO 0);
a,b,c,d,e,f,g: OUT Std_logic);
ENDls49;
ARCHITECTURE behavl_49 OF ls49 IS
SIGNAL s: Std_logic_vector(6 DOWNTO 0);
BEGIN
PROCESS (bi,bl)
BEGIN
IF (bl/='1') AND (bl/='H') THEN
s<=(OTHERS => '0');
ELSE
CASE bi IS
WHEN "0000"=>s<="0111111";
WHEN "0001"=>s<="0000110";
WHEN "0010"=>s<="1011011";
WHEN "0011"=>s<="1001111";
WHEN "0100"=>s<="1100110";
WHEN "0101"=>s<="1101101";
WHEN "0110"=>s<="1111101";
WHEN "0111"=>s<="0100111";
WHEN "1000"=>s<="1111111";
WHEN "1001"=>s<="1101111";
WHEN "1010"=>s<="1110111";
WHEN "1011"=>s<="1111100";
WHEN "1100"=>s<="0111001";
WHEN "1101"=>s<="1011110";
WHEN "1110"=>s<="1111001";
WHEN "1111"=>s<="1110001";
WHEN OTHERS=>s<="0000000";
END CASE;
END IF;
END PROCESS;
a <= s(0);
b <= s(1);
c <= s(2);
d <= s(3);
e <= s(4);
f <= s(5);
g <= s(6);
END behavl49;