求Verilog HDL编程的关于交通灯控制系统的设计与实现

module traffic(clock,reset,red1,yellow1,green1,red2,yellow2,green2);
output red1,yellow1,green1;
output red2,yellow2,green2;
input clock,reset;

reg red1,yellow1,green1;
reg red2,yellow2,green2;
reg [3:0]state;
reg [6:0] count;

parameter st0=0,st1=1,st2=2,st3=3;

always @(posedge clock or posedge reset)
begin
if(reset)
begin
state<=st0;count<=0;
end
else
begin

state<=st0;
count<=count+1;
case(state)
st0:
begin red1<=1'b1;yellow1<=1'b0;green1<=1'b0;
red2<=1'b0;yellow2<=1'b0;green2<=1'b1;
if(count==24) begin state<=st1;count<=0;end
else state<=st0;
end
st1:
begin red1<=1'b1;yellow1<=1'b0;green1<=1'b0;
red2<=1'b0;yellow2<=1'b1;green2<=1'b0;
if(count==4) begin state<=st2;count<=0;end
else state<=st1;
end
st2:
begin red1<=1'b0;yellow1<=1'b0;green1<=1'b1;
red2<=1'b1;yellow2<=1'b0;green2<=1'b0;
if(count==24) begin state<=st3;count<=0;end
else state<=st2;
end
st3:
begin red1<=1'b0;yellow1<=1'b1;green1<=1'b0;
red2<=1'b1;yellow2<=1'b0;green2<=1'b1;
if(count==4) begin state<=st0;count<=0;end
else state<=st3;
end
default:state<=st0;
endcase
end
end

endmodule
如果需要在实验室调通硬件设备，需要再增加分频器。上程序可以实现时序仿真。

module traffic (clock, reset, sensor1, sensor2,

red1, yellow1, green1, red2, yellow2, green2);

input clock, reset, sensor1, sensor2;

output red1, yellow1, green1, red2, yellow2, green2;

// Define the states

parameter st0 = 0, st1 = 1, st2 = 2, st3 = 3,

st4 = 4, st5 = 5, st6 = 6, st7 = 7;

reg [2:0] state, nxstate ;

reg red1, yellow1, green1, red2, yellow2, green2;

// state update
always @(posedge clock or posedge reset)

begin

if (reset)

state = st0 ;

else

state = nxstate;

end

// Calculate the next state and the outputs,

always @(state or sensor1 or sensor2)

begin

red1 = 1'b0; yellow1 = 1'b0; green1 = 1'b0;

red2 = 1'b0; yellow2 = 1'b0; green2 = 1'b0;

case (state)

st0: begin

green1 = 1'b1;

red2 = 1'b1;

if (sensor2 == sensor1)

nxstate = st1;

else if (~sensor1 & sensor2)

nxstate = st2;

else

nxstate = st0;

end

st1: begin

green1 = 1'b1;

red2 = 1'b1;

nxstate = st2;

end

st2: begin

green1 = 1'b1;

red2 = 1'b1;

nxstate = st3;

end

st3: begin

yellow1 = 1'b1;

red2 = 1'b1;

nxstate = st4;

end

st4: begin

red1 = 1'b1;

green2 = 1'b1;

if (~sensor1 & ~sensor2)

nxstate = st5;

else if (sensor1 & ~sensor2)

nxstate = st6;

else

nxstate = st4;

end

st5: begin

red1 = 1'b1;

green2 = 1'b1;

nxstate = st6;

end

st6: begin

red1 = 1'b1;

green2 = 1'b1;

nxstate = st7;

end

st7: begin

red1 = 1'b1;

yellow2 = 1'b1;

nxstate = st0;

end

endcase

end

endmodule