Verilog HDL的有关问题

module tb_pts;//测试文件
// Inputs
reg [7:0] para_in;
reg clock;
reg reset;
// Outputs
wire ser_out;
// Instantiate the Unit Under Test (UUT)
pts uut (
.para_in(para_in),
.clock(clock),
.reset(reset),
.ser_out(ser_out)
);
initial begin
// Initialize Inputs
clock = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
reset=1;
#300
$stop;

// Add stimulus here
end
initial para_in = 8'b11110000;
always #10 clock=~clock;
endmodule

module pts(para_in,clock,reset,ser_out);//顶层文件
input [7:0] para_in;
input reset,clock;
output ser_out;
reg ser_out;
reg [7:0] data;
always@(posedge clock or negedge reset) begin
if(!reset) begin
ser_out <= 1'b0;
data<=para_in;
end
else begin
data<= {data[6:0],data[7]};
ser_out <= data[7];
end
end
endmodule

数据流风格：端口定义就不写了 直接写表达式assign sum = a+b；行为及：定义寄存器 reg sum always@（posedge clk）beginsum <= a+b；门级 and u1（sum，a，b）；

这么简单网上到处都是